1. Technical Field
The present disclosure generally relates to information handling systems (IHS) and in particular to high speed link equalization within information handling systems.
2. Description of the Related Art
As the value and use of information continue to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system (IHS) generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes, thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems frequently communicate information for various applications using high speed serial interfaces. As signal speeds exceed 3-6 Gigabits per second (Gbps), the eye opening at the receiver may be insufficient for dependable operation in most high speed serial link applications that do not deploy advanced equalization techniques. This is due to the fact that ISI (Inter-Symbol Interference) increases as signaling frequency increases, a function of channel reflection, channel loss, and a myriad of other parasitic effects that cumulatively degrade the signal eye. Most High Speed Serial (HSS) interfaces like Serial Advanced Technology Attachment (SATA) 6 Gbps, Peripheral Component Interconnect Express (PCIe) Gen3 8 Gbps, and Serial Attached Small Computer System Interface (SAS) 12 Gbps exhibit this type of degradation. To mitigate these effects, most HSS links utilize power-hungry advanced transmitter (TX) and receiver (RX) equalization techniques. The transmitter techniques include TX equalization such as pre-emphasis, which is the amplification of high frequency components, and de-emphasis, which is the suppression of low frequency components. The pre-emphasis and/or de-emphasis implementations can reduce the ISI to ensure correct signal sampling at the receiver. The receiver techniques involve receiver gain settings such as CTLE (Continuous Linear Time Equalization), and receiver DFE (Decision Feedback Equalization) settings to open up what would otherwise be a closed receiver eye.
Unfortunately however, as signal speeds increase (and/or target channels lengthen), the complexity of the required TX and RX equalization circuitry increases. For example, additional equalization taps are added and more complex circuitry is employed for TX and RX Equalization. The added equalizer taps and increased complexity result in greatly increased channel/link power consumption due to equalization. In fact, in many of today's application specific integrated circuits (ASICs) and other semiconductor devices with high speed serial interfaces, I/O power is more dominant than core power and may reach 50-70% of the total device power consumption.